Portable telecommunications applications place stringent requirements on the design of oscillators, such as voltage-controlled oscillators, in transceivers. The oscillator should have a large tuning range with minimal noise, low power dissipation, low manufacturing cost, and limited susceptibility to crosstalk from other circuits.
The design of varactors, also known as a voltage variable capacitors, is an important aspect of optimizing such oscillators. Both P/N junction semiconductor and metal oxide semiconductor (MOS) capacitors are commonly used. Semiconductor varactor designs are subject to three general considerations: (1) maximize capacitance per unit area occupied by the varactor, (2) maximize the voltage controllable variable capacitance range of the varactor, and (3) maximize the quality factor (Q) of the varactor. Designing and manufacturing semiconductor varactors in which all three considerations have been optimized remains problematic.
For example, certain MOS varactors, may use low doped wells biased with respect to a conductive layer, such as a MOS-type gate, to vary the gate-controlled capacitance in a channel region of the well below the gate. The low doping density of the well, however, has a high series resistance, which in turn degrades the Q of the varactor. Alternatively, the use of a heavily doped channel, while minimizing series resistance may also substantially eliminate voltage controllable variable capacitance.
Previous attempts to resolve this problem have focused on reducing the device dimensions, allowing large perimeters with highly conductive contacts. Such attempts, however, result in devices having a large area to capacitance ratio. Moreover the device has substantial substrate pickup due to the large device area overlapping with the substrate.
Others have attempted to increase the total variable capacitance of P/N junction semiconductor capacitors by implanting P+ into a N-epitaxial layer. Such capacitors are expected, however, to have a small capacitance variation with voltage bias as they implement a pn junction. Increasing their quality factor requires an extra processing step, the growth of a of heavily doped buried layer, that is not commensurate with the CMOS process.
Accordingly, what is needed in the art is a semiconductor varactor with a high capacitance per unit area, high variable capacitance and high quality factor.